1. Technical Field
The present disclosure relates to a method for forming a bit line of a semiconductor device, and more particularly to a method for forming a bit line of a semiconductor device wherein a first opening in a P+ S/D region, and then forming a second opening in an N+ S/D region to prevent increase of the resistance in the N+ source/drain (S/D) region opening during a post etch treatment (PET) for stabilizing the resistance in a P+ S/D region opening.
2. Description of the Related Art
Recently, the size of a unit cell of a semiconductor memory device has decreased continuously due to high integration and large capacity of the semiconductor memory device. As the size of a memory cell of a dynamic random access memory (DRAM) which leads improvements in integration density is decreased, the vertical structure because extremely complex, which calls for a method for increasing an effective area of a capacitor.
A conventional semiconductor device employs a bit line consisting of polycide which is composed of doped polysilicon and tungsten silicide as a data input/output path to increase integration of the device and improve information processing capability.
However, the resistance of the conventional bit line structure in increased as the size of an opening in decreased. In order to solve the foregoing problem, a tungsten bit line having a low resistance value has been introduced.
However, even in the case of the tungsten bit line, the resistance of the opening for forming the bit line shows large changes during a subsequent thermal process. Specifically, since the resistance of a P+ S/D region remarkably increases, a subsequent PET is performed only for the P+ S/D region opening.
The PET is performed after simultaneously forming in the P+ S/D region and the N+ S/D region openings. Thus, while the resistance of the P+ S/D region opening is decreased, the resistance of the N+ S/D region opening is increased.
The resistance of the opening in the N+ S/D region is contrary to the resistance of the opening in the P+ S/D region. Generally, when the resistance of the P+ S/D region opening is reduced and stabilized, the resistance of the N+ S/D region opening is increased, and when the resistance of the N+ S/D region opening is reduced, the resistance of the P+ S/D region opening is increased.
Specifically, when the PET is performed to reduce the resistance of the P+ S/D region opening having an average resistance value of 1200Ω, the resistance of the P+ S/D region opening is stabilized at an average value of 900Ω. However, the resistance of the N+ S/D region opening having a average resistance value of 280 to 300Ω is increased to 450Ω(see FIGS. 1 and 2).
A conventional method for forming a bit line will be described with reference to FIGS. 3a to 3g. 
Referring to FIG. 3a, a conductive layer for a word line (not shown) and a nitride film (not shown) are sequentially formed in a cell region of a semiconductor substrate 1.
Thereafter, the conductive layer for the word line and the hard mask nitride film are pattered via a photolithography process using a mask for a gate electrode to form a word line pattern 4 including a conductive layer pattern 2 for the word line and a nitride film pattern 3 which is a hard mask layer. A spacer 5 is then formed at a sidewall of the word line pattern 4.
A polysilicon layer (not shown) is formed on the entire surface of the resulting structure including the word line pattern 4 and the spacer 5 and then etched to form a plug 6.
Next, P+ S/D region 7 and an N+ S/D region 8 are formed in a peripheral region of the resulting structure, and an interlayer insulating film 9 is then formed on the entire surface of the resulting structure using an oxide film.
Referring to FIG. 3b, openings 11a, 11b and 11c exposing the plug region 6, the P+ S/D region 7 and the N+ S/D region 8, respectively, are formed by etching the interlayer insulating film 9. Thereafter, the opening 11b in the P+ S/D region 7 is subjected to a PET.
Referring to FIG. 3c, a photoresist layer 15 is formed on the entire surface of the resulting structure.
Referring to FIG. 3d, a portion of the photoresist layer 15 on the P+ S/D region 7 is removed to form an opening 11b-1 exposing the P+ S/D region 7.
Opening 11b-1 in the P+ S/D region 7 is subject to a P+ ion implantation process 17 to stabilize the resistance of the opening 11b-1. Thereafter, the photoresist layer 15 is stripped.
Referring to FIG. 3e, a rapid thermal annealing “RTA”process is performed to compensate for damaged oxide film in the P+ S/D region 7 due to the ion implantation process.
When subsequent processes are performed without the RTA process, the damaged portions are etched faster than the undamaged portions during the subsequent cleaning process, and thus a step difference 23 is generated between the P+ ion implant region and the non-implant region, resulting in a bridge 25 (see FIG. 4).
Referring to FIG. 3f, a barrier metal layer 19 is formed on the entire surface of the interlayer insulating film 9 including the opening using Ti/TiN. The Ti layer reacts with the Si substrate by an RTA process to form TiSi2, thereby stabilizing the resistance of the opening.
Thereafter, a tungsten layer 21 is formed on the entire surface of the resulting structure.
Referring to FIG. 3g, the tungsten layer 21 is etched to form a tungsten bit line 21a. 
In accordance with the conventional method for forming the bit line of the semiconductor device, since the openings are simultaneously formed in the P+ S/D region and the N+ S/D region, the resistance of the N+ S/D region opening is increased due to the subsequent PET. Moreover, the RTA process must be introduced in order to compensate for damages of the interlayer insulating film during the additional P+ ion implantation process. These complicate the manufacturing process and decrease the integration and operation speed of the device.